The Peripheral Component Interconnect (PCI) bus has become the universal bus for virtually all high performance microprocessors. The PCI bus is used as an interconnect between boards in a system, as a method of hooking chips together on a board, and as a micro-architecture within chips. The PCI bus is the core of both PowerPC™ architectures and Intel Pentium™/Pentium II™ architectures.
The PCI bus may be part of a backplane, which is an electronic circuit board containing circuitry and sockets into which additional electronic devices on other circuit boards can be plugged. The PCI bus specification (the “Specification”) provides a processor-independent interface to add-in boards, commonly referred to as expansion or adapter boards. Because of alternating current (AC) switching characteristic limitations, a PCI bus is typically limited in both data transfer rate and number of adapter slots supported. Adapter slots are areas on the PCI bus used to couple adapter boards to the PCI bus. Data transfer rate and the number of adapter slots supported in a PCI bus are interdependent, such that achieving an increase in one generally results in a decrease in the other. This data transfer rate is slow for many high performance adapter boards under contemporary workstation requirements. The current 66 Megahertz (MHz) PCI architecture definition provides a peak data transfer rate of 528 megabits per second, but only supports up to 2 slots per PCI bus. Other PCI architecture supporting up to 20 slots per PCI bus may transfer data up to approximately 80 megabits per second.
A CompactPCI™ standard is an adaptation of the Specification for industrial and/or embedded applications. The CompactPCI standard was developed by members of the PCI Industrial Computer Manufacturers Group (PICMG), a consortium of suppliers to the industrial computer and telecommunications markets. The robust nature and high performance of CompactPCI technology makes it attractive to developers of telecom and telephony equipment.
The CompactPCI standard uses industry standard mechanical components and high performance connector technologies to provide an optimized system. The CompactPCI standard provides a data processing system that is electrically and mechanically compatible with the Specification. Rear connectors for CompactPCI boards are numbered J1, starting at the bottom connector, through J5. Use of the connectors has been partially defined by the Specification as to location and signal-pin assignment.
A CompactPCI system is comprised of one or more CompactPCI bus segments. Each CompactPCI bus segment consists of one adapter slot and several peripheral slots. A CompactPCI backplane often incorporates the CompactPCI bus segments for communication and data transfer purposes. CompactPCI backplane slots for CompactPCI boards may be implemented with one or more connectors. Backplane connectors are designated as P1 through P5 corresponding in location to the CompactPCI board's connectors J1 through J5. For example, a CompactPCI board's J1 connector is coupled to a CompactPCI backplane's J1 connector.
In the telephony environment, many individual people may desire to talk to other individuals at the same time. In this common situation, large amounts of traffic are going back and forth requiring a significant data transfer rate capability in the gigabyte per second range. Today, a standard CompactPCI bus is capable of transferring between 33 and 80 megabits per second. Accordingly, there is a need for a reliable and economical CompactPCI bus architecture that is compatible with existing PCI and CompactPCI hardware, and that can transfer much larger amounts of data than currently available, to allow more users to use a single system.
The elements in the drawing figures are not necessarily drawn to scale.